Anritsu MP1763C Error Detector System

The MP1763C is used in combination with the MP1764C or MP1764D Error Detector for 12.5G BER testing. The amplitude of the clock and data signals can be varied from 0.25 to 2 Vp-p while the offset can be adjusted to within ±2 V so that the amplitude and the offset margin can be measured. The clock has a variable delay function so that time dependent characteristics or phase margins of the input clock and data can be measured. An M-series pseudorandom pattern representative of actual conditions or a programmable pattern can be selected as cell data.

1/8 parallel output is standard, and options are available for either 1/4 parallel output or 1/4 differential output. This is the industry's only 12.5G BERT system with differential inputs and ¼ differential outputs required for SAN market device applications.

In addition, a 3.5 inch floppy disk drive is built in for storing preset data, enabling rapid measurements to be performed by simply pressing a key. A GPIB function is provided, enabling automatic or remote measurement via an external controller.

The MP1763C pulse pattern generator is ideal for research and development of high-speed logic, ICs, and digital systems.

• High quality waveform
• Wide frequency range covers STM 0/STS1 to 10 GbE, STM64/STS192, OUT-2, and 4.25G Fibre Channel
• Low FM/PM-noise clock generator
• Differential inputs
• 1/8 parallel output standard, with available options for either 1/4 parallel output or 1/4 differential output
• 8 Mbit programmable pattern corresponding to six frames of STM-64/ STS-192
• Complementary outputs for both data and clock
• Settable amplitudes and offsets for all 8 data outputs with 1/8 speed of the fundamental clock signal